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1 motorola tmos power mosfet transistor device data
? medium power surface mount products ! "
ezfets ? are an advanced series of power mosfets which utilize motorola's high cell density hdtmos process and contain monolithic backtoback zener diodes. these zener diodes provide protection against esd and unexpected transients. these miniature surface mount mosfets feature ultra low r ds(on) and true logic level performance. ezfet ? devices are designed for use in low voltage applications where power efficiency is important. typical applications are liion battery protection, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. ? zener protected gates provide electrostatic discharge protection ? ultra low r ds(on) provides higher efficiency and extends battery life ? logic level gate drive e can be driven by logic ics ? miniature tssop8 surface mount package e saves board space ? i dss specified at elevated temperature ? mounting information for tssop8 package provided maximum ratings (t j = 25 c unless otherwise noted) rating symbol max unit draintosource voltage v dss 20 vdc draintogate voltage (r gs = 1.0 m w ) v dgr 20 vdc gatetosource voltage e continuous v gs 12 vdc drain current e continuous @ t a = 25 c (1) drain current e pulsed i d i dm 3.0 48 adc total power dissipation @ t a = 25 c (1) p d 1.0 watts operating and storage temperature range t j , t stg 55 to 150 c continuous source current (diode conduction) (2) i s 1.25 adc thermal resistance rating symbol max unit thermal resistance e junction to ambient (1) r q ja 125 c/w (1) when mounted on 1 inch square fr4 or g10 board (v gs = 4.5 v, @ 10 seconds) (2) when mounted on fr4 board, t 10 sec. device marking ordering information d1200z device reel size tape width quantity d1200z mbdf1200zel 13 12 mm embossed tape 2000 units designer's data for aworst caseo conditions e the designer's data sheet permits the design of most circuits entirely from the information presented. soa limit curves e representing boundaries on device characteristics e are given to facilitate aworst caseo design. preferred devices are motorola recommended choices for future use and best overall value. designer's, hdtmos and ezfet are trademarks of motorola, inc. tmos is a registered trademark of motorola, inc. thermal clad is a trade- mark of the bergquist company. semiconductor technical data order this document by mbdf1200z/d ? motorola, inc. 1998 ? dual tmos power mosfet 3 amperes 20 volts r ds(on) = 38 m case 948j01 tssop8 motorola preferred device drain1 source1 source1 gate1 1 2 3 4 8 7 6 5 top view drain2 source2 source2 gate2 d s g
2 motorola tmos power mosfet transistor device data electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics draintosource breakdown voltage (cpk 2.0) (1) (3) (v gs = 0 vdc, i d = 0.25 madc) temperature coefficient (positive) v (br)dss 20 e e 10 e e vdc mv/ c zero gate voltage drain current (v ds = 20 vdc, v gs = 0 vdc) (v ds = 20 vdc, v gs = 0 vdc, t j = 125 c) i dss e e e e 5.0 50 m adc gatebody leakage current (v gs = 10 vdc, v ds = 0 vdc) i gss e e 3.0 m adc on characteristics (1) gate threshold voltage (cpk 2.0) (1) (3) (v ds = v gs , i d = 0.25 madc) threshold temperature coefficient (negative) v gs(th) 0.5 e 0.7 2.6 1.0 e vdc mv/ c static draintosource onresistance (cpk 2.0) (1) (3) (v gs = 4.5 vdc, i d = 3.0 adc) (v gs = 2.5 vdc, i d = 1.5 adc) r ds(on) e e 32 44 38 50 m w forward transconductance (v ds = 8.0 vdc, i d = 1.5 adc) (1) g fs 5.0 6.5 e mhos dynamic characteristics input capacitance (v 16 vdc v 0 vdc c iss e 330 470 pf output capacitance (v ds = 16 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss e 270 380 transfer capacitance f = 1 . 0 mhz) c rss e 95 140 switching characteristics (2) turnon delay time (v 8 0 vd i 3 0 ad t d(on) e 19 38 ns rise time (v dd = 8.0 vdc, i d = 3.0 adc, (1) t r e 148 296 turnoff delay time ( dd , d , v gs = 4.5 vdc, r g = 6.0 w ) (1) t d(off) e 350 700 fall time t f e 340 680 gate charge (v 12 vd i 3 0 ad q t e 16 24 nc (v dd = 12 vdc, i d = 3.0 adc, (1) q 1 e 1.5 e ( dd , d , v gs = 10 vdc) (1) q 2 e 2.3 e q 3 e 2.6 e sourcedrain diode characteristics forward onvoltage (i s = 3.0 adc, v gs = 0 vdc) (i s = 3.0 adc, v gs = 0 vdc, t j = 125 c) v sd e e 0.80 0.65 1.0 e vdc reverse recovery time (i 3 0 adc v 0 vdc t rr e 340 e ns (i s = 3.0 adc, v gs = 0 vdc, di s /dt = 100 a/ m s ) (1) t a e 120 e di s /dt = 100 a/ m s) () t b e 220 e reverse recovery storage charge q rr e 1.7 e m c (1) pulse test: pulse width 300 m s, duty cycle 2%. (2) switching characteristics are independent of operating junction temperature. (3) reflects typical values. c pk = max limit typ 3 x sigma (4) repetitive rating; pulse width limited by maximum junction temperature.
3 motorola tmos power mosfet transistor device data typical electrical characteristics i dss , leakage (na) r ds(on) , draintosource resistance (ohms) r ds(on) , draintosource resistance (ohms) 0 0 0.2 0.8 1 0 v ds , draintosource voltage (volts) figure 1. onregion characteristics i d , drain current (amps) i d , drain current (amps) v gs , gatetosource voltage (volts) figure 2. transfer characteristics 0.05 0.06 figure 3. onresistance versus gatetosource voltage i d , drain current (amps) figure 4. onresistance versus drain current and gate voltage 10 1000 figure 5. onresistance variation with temperature v ds , draintosource voltage (volts) figure 6. draintosource leakage current versus voltage v ds 10 v t j = 55 c 25 c 100 c 0.04 2 1 0.02 t j = 25 c 4 8 10 2 1 1.5 2 0.03 023 100 0 4 12 16 20 0.01 0.02 0.04 6 v gs , gatetosource voltage (volts) 1 4.5 v v gs = 2.7 v t j = 25 c r ds(on) , draintosource resistance (normalized) t j , junction temperature ( c) 50 0 50 100 150 0 0.5 1 1.5 2 v gs =4.5 v i d = 3.0 a 125 75 25 25 v gs = 0 v t j = 125 c 100 c 0.6 1.8 v 1.4 v i d = 3.0 a t j = 25 c 0.5 0 0 0.01 0.03 0.05 10000 0.4 3 4 5 6 v 4.5 v v gs = 10v 0.07 246810 0.06 45 100000 1 0.1 25 c 2.5 v 3.5 v 8
4 motorola tmos power mosfet transistor device data power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are deter- mined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculat- ing rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resis- tive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate val- ues from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when cal- culating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements com- plicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a func- tion of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to mea- sure and, consequently, is not specified. the resistive switching time variation versus gate resis- tance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely op- erated into an inductive load; however, snubbing reduces switching losses. figure 7. capacitance variation c, capacitance (pf) v ds , draintosource voltage (volts) 0812 t j = 25 c v gs = 0 v 500 400 100 0 16 c iss c oss c rss 4 600 20 61014 218 200 300
5 motorola tmos power mosfet transistor device data figure 8. gatetosource and draintosource voltage versus total charge figure 9. resistive switching time variation versus gate resistance v gs , gatetosource voltage (volts) q g , total gate charge (nc) 0510 3 15 i d = 3.0 a t j = 25 c v gs 5 1 0 12 0 v ds qt q1 q3 20 v ds , draintosource voltage (volts) t, time (ns) r g , gate resistance (ohms) 1 100 10 v dd = 8.0 v i d = 3.0 a v gs = 4.5 v t j = 25 c t d(on) t r 100 10 t d(off) t f 3 2 15 1000 6 9 q2 4 draintosource diode characteristics the switching characteristics of a mosfet body diode are very important in systems using it as a freewheeling or commutating diode. of particular interest are the reverse re- covery characteristics which play a major role in determining switching losses, radiated noise, emi and rfi. system switching losses are largely due to the nature of the body diode itself. the body diode is a minority carrier de- vice, therefore it has a finite reverse recovery time, t rr , due to the storage of minority carrier charge, q rr , as shown in the typical reverse recovery wave form of figure 11. it is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. therefore, one would like a diode with short t rr and low q rr specifications to minimize these losses. the abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ring- ing. the mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. the diode's negative di/dt during t a is directly con- trolled by the device clearing the stored charge. however, the positive di/dt during t b is an uncontrollable diode charac- teristic and is usually the culprit that induces current ringing. therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. a ratio of 1 is considered ideal and values less than 0.5 are considered snappy. compared to motorola standard cell density low voltage mosfets, high cell density mosfet diodes are faster (shorter t rr ), have less stored charge and a softer reverse re- covery characteristic. the softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell mosfet diode without increasing the current ringing or the noise gen- erated. in addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. 0.6 0 0.5 1 1.5 v sd , sourcetodrain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) v gs = 0 v t j = 25 c 0.8 1 2 2.5 3 0.4 0.2 0
6 motorola tmos power mosfet transistor device data i s , source current t, time figure 11. reverse recovery time (t rr ) di/dt = 300 a/ m s standard cell density high cell density t b t rr t a t rr safe operating area the forward biased safe operating area curves de- fine the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are deter- mined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance general data and its use.o switching between the offstate and the onstate may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded, and that the transition time (t r , t f ) does not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from cir- cuit inductance dissipated in the transistor while in ava- lanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases nonlinearly with an in- crease of peak current in avalanche and peak junction temperature. figure 12. maximum rated forward biased safe operating area 0.1 v ds , draintosource voltage (volts) 1 10 i d , drain current (amps) v gs = 4.5 v single pulse t c = 25 c 10 0.1 10 ms 1 100 100 1 ms dc r ds(on) limit thermal limit package limit 0.01 100 m s
7 motorola tmos power mosfet transistor device data information for using the tssop8 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will selfalign when subjected to a solder reflow process. mm inches 0.0 0.0 0.0 50.0 0.0 0.0 0.0 0.0 0.0 0.0 need correct information for footprint tssop8 power dissipation the power dissipation of the tssop8 is a function of the input pad size. this can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient; and the operating temperature, t a . using the values provided on the data sheet for the tssop8 package, p d can be calculated as follows: p d = t j(max) t a r q ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 125 c, one can calculate the power dissipation of the device which in this case is 1.0 watt. p d = 150 c 125 c 25 c/w = 1.0 watt the 25 c/w for the tssop8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.0 watt using the footprint shown. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using board material such as thermal clad, the power dissipation can be doubled using the same footprint. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
8 motorola tmos power mosfet transistor device data typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 13 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems, but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/in- frared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177 189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 50 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies 100 c 150 c 160 c 170 c 140 c figure 13. typical solder heating profile desired curve for high mass assemblies
9 motorola tmos power mosfet transistor device data package dimensions case 948j01 issue o tssop8 ??? ??? ??? dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane w. section nn seating plane ident. pin 1 1 4 8 5 see detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 8x ref k n n
10 motorola tmos power mosfet transistor device data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; spd, strategic planning office, 141, p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 4321 nishigotanda, shinagawaku, tokyo, japan. 81354878488 customer focus center: 18005216274 mfax ? : rmfax0@email.sps.mot.com touchtone 1 6022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 http://sps.motorola.com/mfax/ home page : http://motorola.com/sps/ mbdf1200z/d ?

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